A field programmable gate array (FPGA), whether alone, or forming an embedded portion of a system-on-chip or other application specific integrated circuit, is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable interconnect or routing network and programmable input/output cells. Programming of the logic blocks, the interconnect resources which make up the network, and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application. The programmability and inherent redundancy of these reconfigurable hardware devices allows for fault tolerant operation of the devices in adaptive computing systems.
The present inventors have recently developed off-line methods of built-in self-testing the array of programmable logic blocks and the programmable interconnect resources in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. Nos. 5,991,907, 6,003,150, 6,108,806, and 6,202,182. In addition to these off-line testing methods, the present inventors have also recently developed methods of testing programmable logic blocks and interconnect resources, including spares, and identifying faulty programmable logic blocks and interconnect resources during normal on-line operation of FPGAs, and fault tolerant operation. These testing, identifying, and fault tolerant operating methods are set out in detail in U.S. Pat. No. 6,256,758 and in pending U.S. application Ser. Nos. 09/405,958, 09/671,853, 09/406,219, 09/611,449, and in 10/189,640. The full disclosures in this patent and these patent applications are incorporated herein by reference.
On-line testing and fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, long-life space missions, telecommunication network routers, or remote equipment in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation to environment changes. In such applications, the adaptive computing systems and reconfigurable hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.
When faults are detected in the resources of these systems, the faulty resources must be quickly identified in order to facilitate efficient reconfiguration of the remaining resources to avoid the faulty resources or preferably to reuse the faulty resources for fault-tolerant operation of the reconfigurable hardware. When the resources are reconfigured for fault tolerant operation, propagation delays along the signal paths may be introduced into the system due. If the propagation delays are in a critical path, a period of a system clock may require adjustment in order to insure proper fault tolerant operation of the reconfigurable hardware. Rather than initially establishing and operating a system clock at a minimum speed selected to work for any possible fault tolerant reconfiguration of the reconfigurable hardware, a need is identified for estimating a worst-case propagation delay introduced by reconfiguring the resources to avoid the faulty resources, and adjusting the period of the system clock if required. In this manner, timing penalties caused by reconfiguration of the reconfigurable hardware for fault tolerant operation may be minimized. Preferably, such an approach to resource utilization would provide for a more gradual degradation of the adaptive computing system hardware, thus extending the useful life of the system while minimizing timing penalties caused by the fault tolerant reconfiguration of the system.